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Tutorial
May 8^th

Conference Day
May 9^th

Location : Flextronics Corp.
                12455 Research Blvd, Austin, TX 78759
                 (just down the road from the Renaissance Hotel)

Mixed-signal DFT and BIST

Teacher – Stephen Sunter (Mentor Graphics)

START TIME - 10AM
LUNCH 12-1PM
WRAP UP - 2PM

Abstract - This tutorial will first analyze recent trends in IC processes and design, and implications for test, then look at trends in testing, such as reducing costs that are increasingly dominated by mixed-signal functions. Next, we’ll discuss trends in ad hoc DFT, and fault simulation, then IEEE DFT standards 1149.1, .4, .6, .8, .10, and P1687. The trend analysis concludes with a review of BIST techniques, focusing on PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, and ‘random’ analog. Next, seven essential principles of practical analog BIST will be presented, with examples. Lastly, we’ll discuss the most-practical DFT techniques, starting with practical analog fault simulation, and progressing from the classic analog bus to mostly-digital oversampling and undersampling methods.

9:30 - 10:00 On site Registration (coffee provided)

Introductions and Agenda

LUNCH - Free lunch sponsored by SiliconAid

~2pm - Class ends

Location : Renaissance Austin Hotel

AGENDA
8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address

Gregg Lowe
(CEO Freescale Semiconductor)

Title - Designing for the Internet of Things

Session 1
9:10 - 9:50 - Presentation 1 - Hank Walker (A&M)
                  Title - Path Delay thru Memories
9:50 - 10:25 - Presentation 2 - Kelvin Ge (Samsung)
                  Title - DFT Challenges in Low-Power CPU Design
10:25 - 11:00 B R E A K

11:00 - 11:35 - Presentation 3 - Paul Tracy (Altera)
                  Title - FPGA Test Challenges and Opportunities
11:35 – 12:15 – Presentation 4 - Technology Spotlight
                  Mentor - 20 min
                  ASSET - 20 min

12:15 - 1:35 LUNCH - Free lunch

Session 2
1:35 – 2:10 - Presentation 5 - Marc Hutner (Teradyne)
                  Title - IP Reuse on ATEs
2:10 – 2:50 - Presentation 6 - Yiorgos Makris (UT Dallas)
                  Title - Semiconductor Security
2:50 - 3:30 - Presentation 7 - Tom Ziaja (Oracle)
                  Title - Memory Char. and Debug via BIST
3:30 - 4:10 B R E A K

Session 3
4:10 – 4:50 - Presentation 8 - John Schulze (AMD)
                  Title - Varying shift rates for throughput
4:50 – 5:30 - Presentation 9 - Phil Bishop (Cadence)
                  Title - Industry overview and outlook
5:30 - 6:30 - Panel Discussion Referee: Jim Johnson
5:30 - 6:30 Happy Hour during Panel

Tutorial May 8^th	Conference Day May 9^th
Location : Flextronics Corp. 12455 Research Blvd, Austin, TX 78759 (just down the road from the Renaissance Hotel) Mixed-signal DFT and BIST Teacher – Stephen Sunter (Mentor Graphics) START TIME - 10AM LUNCH 12-1PM WRAP UP - 2PM Abstract - This tutorial will first analyze recent trends in IC processes and design, and implications for test, then look at trends in testing, such as reducing costs that are increasingly dominated by mixed-signal functions. Next, we’ll discuss trends in ad hoc DFT, and fault simulation, then IEEE DFT standards 1149.1, .4, .6, .8, .10, and P1687. The trend analysis concludes with a review of BIST techniques, focusing on PLL/DLL, ADC/DAC, SerDes/DDR, general I/Os, and ‘random’ analog. Next, seven essential principles of practical analog BIST will be presented, with examples. Lastly, we’ll discuss the most-practical DFT techniques, starting with practical analog fault simulation, and progressing from the classic analog bus to mostly-digital oversampling and undersampling methods. 9:30 - 10:00 On site Registration (coffee provided) Introductions and Agenda LUNCH - Free lunch sponsored by SiliconAid ~2pm - Class ends	Location : Renaissance Austin Hotel AGENDA 8:00 - 8:30 On site Registration (coffee provided) 8:30 - 8:40 Welcomes and introductions 8:40 - 9:10 Key Note Address Gregg Lowe (CEO Freescale Semiconductor) Title - Designing for the Internet of Things Session 1 9:10 - 9:50 - Presentation 1 - Hank Walker (A&M) Title - Path Delay thru Memories 9:50 - 10:25 - Presentation 2 - Kelvin Ge (Samsung) Title - DFT Challenges in Low-Power CPU Design 10:25 - 11:00 B R E A K 11:00 - 11:35 - Presentation 3 - Paul Tracy (Altera) Title - FPGA Test Challenges and Opportunities 11:35 – 12:15 – Presentation 4 - Technology Spotlight Mentor - 20 min ASSET - 20 min 12:15 - 1:35 LUNCH - Free lunch Session 2 1:35 – 2:10 - Presentation 5 - Marc Hutner (Teradyne) Title - IP Reuse on ATEs 2:10 – 2:50 - Presentation 6 - Yiorgos Makris (UT Dallas) Title - Semiconductor Security 2:50 - 3:30 - Presentation 7 - Tom Ziaja (Oracle) Title - Memory Char. and Debug via BIST 3:30 - 4:10 B R E A K Session 3 4:10 – 4:50 - Presentation 8 - John Schulze (AMD) Title - Varying shift rates for throughput 4:50 – 5:30 - Presentation 9 - Phil Bishop (Cadence) Title - Industry overview and outlook 5:30 - 6:30 - Panel Discussion Referee: Jim Johnson 5:30 - 6:30 Happy Hour during Panel