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If the presenter has given approval, presentations will be posted on this page (BELOW). We will possibly add more presentation until June 30th. Recheck later if you don't see the presentation you want.
Location :Austin Crown Plaza Hotel (I35 & 290)
(Click on picture for bio)
9:50 - 10:30 - Presentation 2 - Tom Ziaja (Oracle)
Title - Memory Test and Repair
10:30 - 11:00 B R E A K
11:00 12:15 Presentation 3 - Technology Spotlights
Mentor Graphics - 20 min
Optimal - 20 min
SiliconAid - 20 min
12:15 - 1:35 LUNCH - Free lunch
1:35 2:15 - Presentation 4 - Stephen Sunter (MGC)
Title - ISO 26262 (Automotive Safety)
2:15 2:55 - Presentation 5 - David Whetstone (Goepel)
Title - Functional vs JTAG Testing
2:55 - 3:30 B R E A K
3:30 4:10 - Presentation 6 -Prof. D.Walker (A&M)
Title - Supply Noise Control During Delay Testing
4:10 4:50 - Presentation 7 - Teresa McLaurin (ARM
Title - DFT Solutions - ARMฎ MaliTM -Mimir GPU"
5:00 - 6:00 - Panel Discussion Referee: Jim Johnson
5:00 - 6:00 Happy Hour during Panel
Location :Holiday Inn Mid-Town (6000 Middle Fiskville Rd - a few miles from Crowne Plaza)
Teacher - Thecla Chomicz (NXP)
Testing large analog subsystems within even larger digital SoCs requires an integrated Design for Test and Test Engineering approach from day one. This presentation will identify how to align the overall test strategy to various expectations of test across multiple disciplines. These expectations include testing for manufacturing anomalies, validating against industry specifications, reducing test costs and the ability to debug issues in Silicon. Once the various test expectations are defined, the analog sub-system is analyzed to expose critical components needed for test access and in-application observation. Lastly, a method that allows for quick turn test development targeting several different environments including simulation, production test and bench top testing will be discussed.
9:00 - 9:30am On site Registration (coffee provided)
~4pm - Class ends
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