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Tutorial
May 2nd

Conference Day
May 3rd

TITLE : Debug and Failure Analysis

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9:30 - 10:00 On site Registration (coffee provided)

Instructor - Robert Aitken (ARM)

Debug and Failure Analysis

  • Introductions and Agenda
  • LUNCH - Free lunch sponsored by SiliconAid

This tutorial covers the basics of chip-level diagnosis and debug, including discussions of the nature of the physical defects that can occur, electrical diagnosis tools and algorithms for logic, memory, and scan chains, diagnosis of timing failures, step-by-step debug strategies for failing silicon, and design-for-debug techniques.

4pm -  Class end

 

 

 

 

 

 

 

 

 

 

 

 

 

 


8:00 - 8:30 On site Registration (coffee provided)
 8:30 - 8:40 Welcomes and introductions
 8:40 - 9:10 Key Note Address – Ty Garibay (Altera Corp. -  VP ) Title – The Coming Silicon Convergence

Session 1 
9:10 - 9:50 - Presentation 1 - Cinda Flynn (Freescale)
                   Title – Test Cost Evaluations
 9:50 - 10:30 - Presentation 2 - Han Ta (Cisco)
                   Title – Bridge Gap Between Test and ATE
10:30 - 11:10  B R E A K
 11:10 – 12:10 – Sponsor Presentations  - (20 min each)
                   
 12:10 - 1:30 LUNCH - Free lunch
Session 2  
1:30 – 2:10 - Presentation 4 - Pete Patton (ASE)
                   Title – ATE and Test Demands
 2:10– 2:50 - Presentation 5 -  Jacob Abraham (UT)
                   Title – On Chip Instruments
 2:50 - 3:30 - Presentation 6  - Grady Giles (AMD)
                   Title – Scan di/dt Mitigation

3:30 - 4:10  B R E A K
Session 3         
4:10 – 4:50 - Presentation 7 - Gordon Roberts (McGill University)
                   Title – Signal Processing Impacts on Analog and MS Test
4:50 – 5:30 - Presentation 8 - Teresa McLaurin (ARM)
                   Title – Structural Patterns for At Speed Test
 5:30 - 6:30 - Panel Discussion              Referee: Jim Johnson
 5:30  - 6:30 Happy Hour during Panel